Field of the Invention
The present invention relates to a method for producing a semiconductor device and a semiconductor device.
Description of the Related Art
For semiconductor integrated circuits, in particular, integrated circuits employing MOS transistors, the degree of integration has been continuously increased. With this increase in the degree of integration, the size of MOS transistors in such integrated circuits has been reduced to the order of nanometers. In such small MOS transistors, leak current is difficult to suppress. Thus, from the standpoint of ensuring a sufficiently large current, reduction in the circuit area is difficult to achieve, which has been problematic. In order to address this problem, a Surrounding Gate Transistor (hereafter, referred to as an “SGT”) has been proposed, the SGT having a structure in which a source, a gate, and a drain are disposed so as to be perpendicular to a substrate and a gate electrode is disposed so as to surround a pillar-shaped semiconductor layer (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
In existing SGT production methods, a mask for defining a silicon pillar is used to form the silicon pillar including a pillar-shaped nitride-film hard mask; a mask for defining a planar silicon layer is used to form the planar silicon layer under the silicon pillar; and a mask for defining a gate line is used to form the gate line (for example, refer to Japanese Unexamined Patent Application Publication No. 2009-182317). In other words, three masks are used to form the silicon pillar, the planar silicon layer, and the gate line.
In production of existing MOS transistors, in order to successfully perform a metal-gate process and a high-temperature process, a metal-gate last process of performing the high-temperature process and subsequently forming a metal gate is employed for actual products (IEDM2007 K. Mistry et. al, pp 247-250). Specifically, a gate is formed of polysilicon; an interlayer insulating film is then deposited; chemical mechanical polishing is then performed to expose the polysilicon gate; the polysilicon gate is etched; and metal is then deposited. Thus, also for SGTs, in order to successfully perform the metal-gate process and the high-temperature process, the metal-gate last process of performing the high-temperature process and subsequently forming the metal gate needs to be employed.
When metal is deposited to fill a hole in which the upper portion is narrower than the lower portion, the upper portion of the hole is first filled with the metal, so that the lower portion is left unfilled.
Existing MOS transistors employ a first insulating film in order to decrease the parasitic capacitance between the gate line and the substrate. For example, in FINFET (IEDM2010 C C. Wu, et. al, 27.1.1-27.1.4), a first insulating film is formed around a fin-shaped semiconductor layer and the first insulating film is subjected to etch back to expose the fin-shaped semiconductor layer, so that the parasitic capacitance between the gate line and the substrate is decreased. Thus, SGTs also need to employ a first insulating film in order to decrease the parasitic capacitance between the gate line and the substrate. Since SGTs include a fin-shaped semiconductor layer and also a pillar-shaped semiconductor layer, how to form the pillar-shaped semiconductor layer needs to be considered.
When the fin-shaped semiconductor layer has high parasitic resistance, the current driving force of the transistor decreases.